1. Field of the Invention
The present invention relates to a communication system that performs a serial transmission of data between a communication control means and a plurality of sub-communication means, an image forming apparatus provided with this communication system, an initialization method, a trouble compensation method, and a storage medium that contains a program for executing the method.
2. Description of Related Art
There is known a serial communication apparatus, in which a transmitting apparatus and a receiving apparatus operate independently of one another. To reset the receiving apparatus in this serial communication apparatus, there is provided a special reset signal line between the transmitting apparatus and the receiving apparatus, and a reset signal is transmitted from the transmitting apparatus to the receiving apparatus through the reset signal line to thereby reset the receiving apparatus (first prior art).
Another serial communication apparatus has been proposed (second prior art). FIG. 1 is a block diagram showing the construction of an example of this serial communication system. In FIG. 1, the serial communication system is constructed in such a manner that a communication controller 402, a sub-communication IC 410 connected to a motor driver 412 for driving a motor 413, and a sub-communication IC 411 to which a plurality of sensors 414 are connected are cascade-connected through a pair of communication lines comprised of a synchronization line (CLK) and a data (DATA) line for serial transmission.
Eight sub-communication ICs at the maximum can be connected to a pair of communication lines, and a proper address (address 0, address 1, . . . , address 7) can be designated for each sub-communication IC. In the example of FIG. 1, two sub-communication ICs 410, 411 are connected to the pair of communication lines. There are eight data registers 0-7 in the communication controller 402, and these data registers 0-7 correspond to the proper addresses (address 0-address 7) of the sub-communication ICs, respectively.
A serial communication control part 403 of the communication controller 402 controls the transmission to the sub-communication ICs 410, 411 and the receipt from the sub-communication ICs 410, 411. The communication controller 402 transmits or receives data to or from the sub-communication ICs 410, 411 corresponding to the data registers. The data are transmitted from the communication controller 402 to the sub-communication ICs 410, 411 through a transmitting buffer 405 and a shift register 406, and the data are received from the sub-communication ICs 410, 411 to the communication controller 402 through a shift register 408 and a receiving buffer 407. A core part 404 is capable of controlling the serial communication control part 403 according to a program which has been prepared in advance.
FIG. 2 is a block diagram showing the construction of an example of the serial communication system in FIG. 1, which is built in an image forming apparatus 500 such as a copying machine. In FIG. 2, a host CPU 501 is connected to a communication controller 502 through an address bus, a data bus and a control signal bus. A sub-communication IC 503 to which is connected a motor driver 507 for driving a motor 508 arranged at a proper position in the apparatus, a sub-communication IC 504 to which are connected a plurality of drivers 509 for driving a plurality of clutches 510, and sub-communication ICs 505, 506 to which are connected a plurality of sensors 511, 512 are connected to the communication controller 502 through a pair of communication lines. FIG. 2 does not illustrate a power supply voltage or ground.
In accordance with a transmitting command or a receiving command from the host CPU 501, data are transmitted between the communication controller 502 and the sub-communication ICs 503-506. Regardless of the positions of the sub-communication ICs 503-506 in the apparatus, a proper address (address 0, address 1, address 2, . . . ) is designated for each sub-communication IC. The communication controller 502 designates the address in a communication frame (pulse train) to thereby transmit and receive the data to and from the sub-communication IC corresponding to the address.
There will now be explained the outline of the operation of the serial communication system constructed as above. To transmit predetermined phase data to run the motor 508, the host CPU 501 sets a transmission flag (not shown in the drawing) in the communication controller 502, and writes the transmission data in a data register 0. When the transmission data is written in the data register, the communication controller 502 transmits a pulse train of a predetermined frequency to a CLK line. In synchronism with the pulse train, the communication controller 502 and the sub-communication IC 503 transmit the data in the data register 0 according to a transmission data format shown in FIG. 3.
In FIG. 3, the sub-communication IC 503 recognizes the start of the transmission at a first fall of CLK transmitted from the communication controller 502, and confirms whether the communication controller 502 transmits a start bit of “L” to a DATA line at a next rise of CLK. According to data received at a next fall of CLK, the sub-communication IC 503 determines whether to perform data transmission (“L”) or data receipt (“H”).
Data A0-A2 of next three clocks are address bits, and the communication controller 502 transmits addresses A0-A2 onto the DATA line. If the addresses A0-A2 are the address of the sub-communication IC 503, the sub-communication IC 503 captures data of eight bits (D7-D0) on the DATA line, which are transmitted in synchronism with subsequent CLKs.
At a next fall of CLK, the sub-communication IC 503 captures parity data (PA) transmitted from the communication controller 502 at the next fall of CLK, and compares the captured parity data with parity data (PA) which is calculated by the sub-communication IC 503 from the data (D7-D0). If the parity data correspond to one another, the data (D7-D0) are determined as being effective, and ACK (“L”) is transmitted to the communication controller 502. If the parity data do not correspond to one another, the sub-communication IC 503 determines the data (D7-D0) as being ineffective and transmits ACK (“H”) to the communication controller 502.
At a rise of CLK, the communication controller 502 receives the ACK. If the ACK is “L”, the communication controller 502 transmits a stop bit of “L” at a fall of CLK after the next. If the ACK is “H”, the communication controller 502 transmits a stop bit of “H” at a fall of CLK after the next. The designated sub-communication IC recognizes the stop bit at a rise of the CLK. If the stop bit is “L”, the sub-communication IC outputs data, and if the stop bit is “H”, the sub-communication IC does not output data. In the above sequence, the data are transmitted between the communication controller 502 and the sub-communication IC 503 to run the motor 508.
There will now be explained the data receiving operation for reading a value of the sensor 511 connected to the sub-communication IC 505. To receive the data, the host CPU 101 sets a receiving flag (not shown in the drawing) in the communication controller 502. When the receiving flag is set, the communication controller 502 transmits a pulse train of a predetermined frequency to the CLK line. In synchronism with the pulse train, the communication controller 502 and the sub-communication IC 505 receive the data according to a receiving data format shown in FIG. 4.
In FIG. 4, the sub-communication IC 505 recognizes the start of the transmission at a first fall of CLK transmitted from the communication controller 502, and confirms whether the communication controller 502 transmits a start bit of “L” to the DATA line at a next rise of CLK. According to data received at a next fall of CLK, the sub-communication IC 505 determines whether to perform data transmission (“L”) or data receipt (“H”).
Data A0-A2 of next three clocks are address bits, and the communication controller 402 transmits addresses A0-A2 onto the DATA line. If the addresses A0-A2 are the address of the sub-communication IC 505, the sub-communication IC 505 transmits the data of the sensor 511 to the communication controller 502 from a next CLK. The designated sub-communication IC 505 transmits data of eight bits (D7-D0) onto the DATA line at a fall of CLK, and the communication controller 502 captures the data (D0-D7) at a rise of CLK.
At a next rise of CLK, the communication controller 502 captures parity data (PA) transmitted from the sub-communication IC 505 at the next fall of CLK, and compares the captured parity data with parity data (PA) which is calculated by the communication controller 502 from the data (D7-D0). If the parity data correspond to one another, the data (D7-D0) are determined as being effective, and if the parity data do not correspond to one another, the data (D7-D0) are determined as being ineffective. In the above sequence, the data are transmitted to the sub-communication IC 505 to read the value of the sensor 511.
There will now be explained how the sub-communication ICs 503-506 are reset by the communication. The host CPU 501 sets a communication reset flag (not shown in the drawing) in the communication controller 502. When the communication flag is set, the communication controller 502 transmits a predetermined reset pulse train as shown in FIG. 5 to the CLK line and the data line. The sub-communication ICs 503-506 are reset immediately upon the receipt of the reset pulse train.
Accordingly, many motors and sensors arranged in many parts of the apparatus can be operated and the information can be read through four signal lines that are cascade-connected. In the above example according to the prior art, one address is comprised of 8 bits, and the information of eight bits is transmitted between the communication controller and the sub-communication ICs. This, however, may be changed to an optimum structure according to rules of a communication data format. If there are provided a plurality of communication controller functions, an increased number of sub-communication ICs can be provided by increasing signal lines corresponding to the communication controller functions. Moreover, since the sub-communization ICs can be reset by the communication, this eliminates the necessity of providing a special reset signal line between the communication controller and the sub-communication ICs.
The above-described prior arts, however, have disadvantages as stated below.
According to the first prior art, a special reset signal line is needed to transmit the reset signal in order to reset the communication controller.
According to the first prior art, when the reset signal line is broken or the like in the case where the reset signal is transmitted through the special reset signal line, the power is supplied to loads connected to the receiving sub-communication ICs although the situation is abnormal. This makes it impossible to protect the loads.
According to the second prior art, in an abnormal state wherein the host CPU runs out of control or a communication reset signal is continuously supplied to the communication controller, or when the power supply is off, the communication reset signal may not be normally transmitted to the sub-communication ICs. This makes it impossible to protect the loads at the receiving side.